Timing improvements #59
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This reverts commit 431087a.
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This PR includes timing improvements that were discussed in this presentation:
https://indico.cern.ch/event/1387937/#13-timing-updates
In particular, the new unbinned memory adapted from Thomas's work is used by default, and additional shift registers have been added for some of the input signals (ap_start and bx_V) to the processing modules.
ETA: The updates to the unbinned memory module have been reverted for now. To be revisited once the outstanding dual-FPGA work is merged.